The present invention is related to systems and methods for processing information, and more particularly to systems and methods for processing a series of encoded bits.
Data transfer systems typically include a receiver that converts an analog input into a stream of digital bits representing the analog input. For example, in a hard disk drive system, digital information is converted to an analog signal that is stored as a magnetic signal on a storage medium. The magnetic information is sensed and converted to an analog signal. The received analog signal is converted back to digital information representing the digital information originally provided to the storage medium. As another example, a wireless communication system involves a transmitter that receives digital information, and converts it to an analog signal that is transmitted. The analog signal is received and converted back to the original digital information that was originally prepared for transmission.
Turning to FIG. 1, a prior art system 100 for converting a received analog signal into corresponding digital information is depicted. System 100 includes an analog to digital converter that converts an analog input 105 into a series of digital sample values that are provided to a filter 120 that is synchronized to a sample clock 125. Filter 125 provides a real output 130 that is provided to a Viterbi decoder 140. Viterbi decoder 140 is synchronized to sample clock 125, and performs a detection process that yields an ideal output 145. Ideal output 145 and real output 130 are both provided to a comparator 150 that yields an error value 155. Error value 155 is provided to a clock adjustment circuit 160. Clock adjustment circuit 160 receives a reference clock 165 and is operable to provide sample clock 125. Thus, sample clock 125 is adjusted based upon a combination of real output 130 and ideal output 145.
There is a desire to increase the bandwidth of data decoding systems such as system 100. One approach is to increase the rate of sample clock 125 which allows for receiving and converting a higher bandwidth analog input 105. Such an approach results in considerable power consumption by Viterbi decoder 140. Further, depending upon the available technology, Viterbi decoder 140 cannot be designed to accommodate a large increase in sample clock 125. In some cases, Viterbi decoder 140 is designed as a group of parallel decoders with cross-linked information. Such an approach increases the size of the Viterbi trellis by parallelizing the algorithm and looking deeper into the trellis on each clock cycle. While this allows an effective reduction in the clock rate for the same throughput, it comes at, among other things, a substantial increase in the amount of logic required to implement Viterbi decoder 140.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for processing a received signal.